FIG. 1 is a block diagram of an imager 100. The imager 100 includes a plurality of pixels 102 for sensing a level of incident light. The pixels 102 are arranged into rows and columns to form a pixel array 101. Each pixel 102 produces an indication of the level of incident light in the form of two signals, namely, a reset signal Vrst and a photo signal Vsig.
The imager 100 also includes a timing and control circuit 150. The timing and control circuit 150 operates a row decoder 120, row driver 110, column decoder 170, a column memory 165, and a column parallel analog to digital converter (ADC) 160. The row decoder 120 and row driver 110 are operated to select a row within the pixel array 101. The column parallel ADC 160 is operated to receive pixel signals from the row selected by the row decoder 120 and driver 110. The column parallel ADC 160 samples and stores the pixel output signals Vrst and Vsig and, for each pixel in the selected row, subtracts them to form an analog pixel signal (Vrst−Vsig), and produces a equivalent digital value, which is stored in the column memory 165. The column parallel ADC 160 supplies these digital values in sequence to the image processor 180. The image processor 180 may perform additional processing operations on the digital signals such as, for example, color correction, and provides an image output. The output of the image processor 180 is routed to an output circuit 190, which can output the processed result to a storage device, screen, or printer.
Existing circuits for storing and digitizing pixel signals are relatively complex, making designs using existing circuits difficult to economically scale the existing design to large pixel arrays. Additionally, when the existing circuits are replicated, each circuit may exhibit an offset in its output, resulting in fixed pattern noise. Accordingly, there is a need for a more efficient circuit for receiving and digitizing pixel signals. Additionally, there is a need for such a circuit to be capable of automatically calibrating its output in order to minimize fixed pattern noise.